1. Field of the Invention
The present invention relates in general to frequency multiplier circuits, and a frequency multiplier circuit in which a clock signal of a frequency of double that of an input clock signal is generated at a point of time that the input clock signal is synchronous with a signal obtained by delaying the input clock signal by half a period of the input clock signal, the generated double frequency clock signal is transited at a point of half a period of the input clock signal, and clock signals of frequencies of n times that of the input clock signal may be generated and transited at positions of 1/n times a period of the input clock signal to adjust a duty factor, where n is 2, 3, 4, . . . .
2. Description of the Prior Art
In designing a system, a delay circuit or a phase locked loop (PLL) circuit may generally be used to obtain a signal providing a position of 1/4 a period of a clock signal for the system.
Referring to FIG. 1, there is shown a block diagram of a conventional frequency multiplier circuit. As shown in this drawing, the conventional frequency multiplier circuit comprises a frequency divider 1 for dividing a frequency of a reference clock signal ref by n, a phase detector 2 for comparing a frequency of an output signal from the frequency divider 1 with a frequency of n*m times that of the reference clock signal ref and generating a pulse train in accordance with the compared result, a low pass filter 3 for removing a high-frequency component from an output signal from the phase detector 2, a voltage controlled oscillator 4 for generating an oscillating frequency in response to an output voltage from the low pass filter 3, and a frequency divider 5 for dividing an output frequency from the voltage controlled oscillator 4 by m and outputting the resultant clock signal to the phase detector 2, the clock signal having the frequency of n*m times that of the reference clock signal ref, where n and m are a degree and a multiple in dividing the reference clock signal ref, respectively.
The operation of the conventional frequency multiplier circuit with the above-mentioned construction will hereinafter be described.
At an initial state, the voltage controlled oscillator 4 outputs an initial frequency signal to the frequency divider 5. Then, the frequency divider 5 outputs a signal of a frequency of m times that of the initial frequency signal from the voltage controlled oscillator 4 to the phase detector 2.
At this time, the frequency divider 1 divides the frequency of the reference clock signal ref by n and outputs a signal of a frequency of n times that of the reference clock signal ref to the phase detector 2. The phase detector 2 compares the frequency of the output signal from the frequency divider 1 with the frequency of the output signal from the frequency divider 5. As a result of the comparison, if the frequency of the output signal from the frequency divider 1 is higher than that of the output signal from the frequency divider 5, the phase detector 2 outputs a positive pulse train. On the contrary, if the frequency of the output signal from the frequency divider 1 is lower than that of the output signal from the frequency divider 5, the phase detector 2 outputs a negative pulse train.
The low pass filter 3 filters the output signal from the phase detector 2 to pass a low-frequency component therefrom. Then, the low pass filter 3 adjusts the passed low-frequency component to adjust a level of its output voltage. Namely, upon receiving the positive pulse train from the phase detector 2, the low pass filter 3 increases the level of its output voltage. On the contrary, receiving the negative pulse train from the phase detector 2, the low pass filter 3 reduces the level of its output voltage.
As the low pass filter 3 increases or reduces the level of its output voltage, the voltage controlled oscillator 4 increases or reduces the oscillating frequency. The resultant oscillating frequency from the voltage controlled oscillator 4 is applied to the frequency divider 5.
With the above operation repeatedly performed, the output signals from the frequency dividers 1 and 5 become the same in phase at a certain time point. In this case, the output of the phase detector 2 becomes "0" and the oscillating operation of the voltage controlled oscillator 4 becomes stable as the output signal therefrom is circulated through the frequency divider 5. As a result, the frequency of the output signal from the voltage controlled oscillator 4 is m time that of the reference clock signal ref.
However, the above-mentioned conventional frequency multiplier circuit has a disadvantage in that it may have a faulty operation under the great influence of a temperature variation or a process parameter in the case of employing a delay circuit. Also, in the case of employing a PLL, the conventional frequency multiplier circuit is desirable to perform an accurate operation, but has the disadvantage that resistors and capacitors must additionally be provided in the outside of the PLL chip, resulting in the increase in the size of the entire circuit and the manufacturing cost.
In other words, the conventional frequency multiplier circuit requires essentially the resistors and the capacitors because it is an analog circuit. This requirement of the conventional frequency multiplier circuit results in the increase in the size and cost of a semiconductor chip to be manufactured. Also, much time is required from the initial step till the stabilization in the frequency of the output signal. Further, a tuning work is difficult to perform in designing the semiconductor chip. Moreover, the temperature variation or the process parameter of the manufactured semiconductor chip has the great effect on the conventional frequency multiplier circuit, resulting in the faulty operation.